Realistic Fault Modeling For Vlsi Testing

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Realistic Fault Modeling for VLSI Testing
Language: en
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Authors: Carnegie-Mellon University. SRC-CMU Research Center for Computer-Aided Design
Categories: Electronic circuits
Type: BOOK - Published: 1987 - Publisher:

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Abstract: "Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be signif
VLSI Fault Modeling and Testing Techniques
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VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in t
Delay Fault Testing for VLSI Circuits
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Authors: Angela Krstic
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Type: BOOK - Published: 2012-12-06 - Publisher: Springer Science & Business Media

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In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, t
Hierarchical Modeling for VLSI Circuit Testing
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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the alm
Realistic Fault Modeling and Quality Test Generation of Combined Delay Faults
Language: en
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Authors: Ajaykumar A. Thadhlani
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