Wafer Level Testing And Test During Burn In For Integrated Circuits

Download or read book Wafer-Level Testing and Test During Burn-In for Integrated Circuits written by Sudarshan Bahukudumbi and published by Artech House. This book was released on 2010 with total page 198 pages. Available in PDF, EPUB and Kindle. Book excerpt: Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.